I am a third-year PhD student at the School of Computing, National University of Singapore, advised by Professor Prateek Saxena and Professor Umang Mathur.

Recently, I have developed an interest in programming language design and formal verification.

I am a member of the KISP Lab and the FOCS Lab.

Currently, I am working on tools and techniques for safer yet expressive hardware design. This work started with Anvil, a new hardware description language that guarantees timing safety at compile time.

You can learn other things about me here.

Feel free to reach out through any of the platforms below:

Or in person at:

B51, Security Lab, COM3
School of Computing,
National University of Singapore
11 Research Link, Singapore 119391

For a detailed CV, including past experience, ongoing projects, and manuscripts under review, please reach out to me. Here is a brief rundown of my recent academic activities.

Education

• PhD in Computer Science (2024 - Present)
  School of Computing, National University of Singapore
  Advisors: Prof. Prateek Saxena, Prof. Umang Mathur
• Bachelor of Technology in Electrical Engineering (2020 - 2024)
  Indian Institute of Technology, Kharagpur
  Micro Specialization in Embedded Control Modelling Software and Design

Skills and Interests

• Programming Languages: C, C++, Python, OCaml, Rust, SystemVerilog
• Tools & Technologies: Anything with documentation :P
• Research Interests: PL/Formal Methods, Computer Architecture, Security, Operating Systems-

Published Works

(* indicates equal contribution)

1. Jason Zhijingcheng Yu*, Aditya Ranjan Jha*, Umang Mathur, Trevor E. Carlson, and Prateek Saxena. “Anvil: A General Purpose Timing-Safe Hardware Description Language.” In Proceedings of the 31st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2026).

Other Roles

• Artefact Review Committee Member for: PLDI 2026 , CAV 2026, ASPLOS 2026 (Summer)
• Teaching Assistant for: CS3235 Computer Security : (2024-2025),(2025-2026)