For a detailed CV, including past experience, ongoing projects, and manuscripts under review, please reach out to me. Here is a brief rundown of my recent academic activities.

Education

PhD in Computer Science 2024 – Present
School of Computing, National University of Singapore
Advisors: Prof. Prateek Saxena, Prof. Umang Mathur
B.Tech. in Electrical Engineering 2020 – 2024
Indian Institute of Technology, Kharagpur
Micro Specialization in Embedded Control Modelling Software and Design

Publications

* indicates equal contribution

  1. Aditya Ranjan Jha*, Jason Zhijingcheng Yu*, Umang Mathur, and Prateek Saxena. “A Type System for Communication-Safe Hardware Design.” To appear at Symposium on Principles of Programming Languages (POPL 2027).
    • Short paper titled “Language-based Hardware Communication Safety and Liveness” at the Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2026), co-located with ASPLOS 2026. [pdf]
  2. Jason Zhijingcheng Yu*, Aditya Ranjan Jha*, Umang Mathur, Trevor E. Carlson, and Prateek Saxena. “Anvil: A General Purpose Timing-Safe Hardware Description Language.” In Proceedings of the 31st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2026). [doi] [code] [website] [docs]

Service

  • Artifact Evaluation Committee POPL 2027, PLDI 2026, CAV 2026, ASPLOS 2026 (Reserved)
  • Sub/External Reviewer SETTA 2026
  • Teaching Assistant CS3235 Computer Security (AY 2024–25, AY 2025–26)

Skills and Interests

  • Research PL/Formal Methods, Computer Architecture, Security, Operating Systems
  • Languages C, C++, Python, OCaml, Rust, SystemVerilog
  • Tools Anything with documentation :P